1. Field of the Disclosure
Generally, the present disclosure relates to the field of sophisticated integrated circuits and semiconductor devices and, more particularly, to FinFET devices with enlarged channel regions.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors (FETs), wherein, for many types of complex circuitry, metal-oxide-semiconductor (MOS) technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of N-channel transistors and P-channel transistors are formed on a substrate including a crystalline semiconductor layer.
Although significant advantages may be obtained with respect to performance and controllability of sophisticated planar transistor architectures, in view of further device scaling, new transistor configurations have been proposed in which a “three-dimensional” architecture may be provided in an attempt to obtain a desired channel width, while at the same time maintaining superior controllability of the current flow through the channel region. To this end, so-called FinFETS have been proposed in which a thin sliver or fin of silicon may be formed in a thin active layer of a silicon-on-insulator (SOI) substrate, wherein at least on both sidewalls of the fin, and possibly on a top surface thereof, a gate dielectric material and a gate electrode material may be provided, thereby realizing a “double gate” or “tri-gate” transistor, the channel region of which may be fully depleted. Typically, in sophisticated applications, the width of the silicon fins is on the order of 10-20 nm and the height thereof is on the order of 30-40 nm.
Thus, FinFET transistor architectures, which may also be referred to herein as multiple gate transistors, may provide advantages with respect to increasing the effective coupling of the gate electrode to the various channel regions without requiring a corresponding reduction in the thickness of the gate dielectric material. Moreover, by providing this non-planar transistor architecture, the effective channel width may also be increased so that, for given overall transistor dimensions, an enhanced current drive capability may be accomplished. For these reasons, great efforts have been made in order to provide enhanced transistor performance on the basis of non-planar transistor architectures.
It is noted that both planar and three-dimensional transistor devices can be formed according to the replacement gate approach or the gate first approach. In the replacement gate technique, a so-called “dummy” or sacrificial gate structure is initially formed and remains in place as many process operations are performed to form the device, for example, the formation of doped source/drain regions, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials. At some point in the process flow, the sacrificial gate structure is removed to define a gate cavity where the final HK/MG gate structure for the device is formed. Using the gate first technique, on the other hand, involves forming a stack of layers of material across the substrate, wherein the stack of materials includes a high-k gate insulation layer (with a dielectric constant k larger than 5), one or more metal layers, a layer of polysilicon, and a protective cap layer, for example, silicon nitride. One or more etching processes are performed to pattern the stack of materials to thereby define the basic gate structures for the transistor devices. Formation of an e-fuse in accordance with the present disclosure may be readily integrated in both the replacement gate process flow and gate first process flow.
FIGS. 1a-1c illustrate a conventional process of manufacturing a FinFET device. In the shown example, a gate first approach is described. As shown in FIG. 1a, semiconductor fins 110 are formed on a base layer 102. The base layer 102 may be a buried oxide layer formed on a semiconductor bulk substrate 101 of an SOI wafer. Alternatively, the base layer 102 may be a semiconductor layer, for example, it may represent part of a semiconductor bulk substrate 101. The semiconductor material of the fins 110 may be formed on the basis of complex epitaxial growth techniques. The fins 110 may be formed with lateral dimensions in accordance with the overall design rules. A cap layer 112 may be provided prior to patterning the fins 110 if the top surfaces of the fins 110 are not to be used as channel regions. The cap layer 112 may comprise or consist of silicon oxide or silicon nitride, for example. Furthermore, prior to or after patterning the fins 110, a basic dopant profile may be established, for instance with respect to defining the basic conductivity type of the fins and the like. This may be accomplished by implantation techniques and/or by incorporating a desired dopant species during the epitaxial growth process for forming the material for the fins 110. Next, a gate electrode structure is formed (see FIG. 1b), for instance, by forming an appropriate gate dielectric material 121, such as a silicon dioxide or a high-k dielectric material, which may be accomplished by sophisticated oxidation techniques and the like, followed by the deposition of the gate electrode material 120, such as polysilicon. The gate electrode structure may have appropriate lateral dimensions so as to cover a central portion of the fins 110 and thereby define corresponding channel lengths for each of the fins 110.
After planarizing the electrode material, which may also comprise providing appropriate materials for forming a hard mask, adjusting the overall optical characteristics on the basis of an anti-reflective coating (ARC) material and the like, the electrode material may be patterned by using a resist mask obtained by lithography and performing an appropriate etch sequence, wherein a high degree of etch selectivity between the gate electrode material and the gate dielectric material may provide for integrity of the end portions of the fins 110. For example, well-established yet complex process techniques are available for etching polysilicon material selectively to silicon dioxide.
After forming the gate electrode structure comprising the gate electrode material 120 and the gate dielectric material 121, drain and source areas may be formed, for instance, by ion implantation, which may include the deposition of a spacer material and patterning the same, if required, while, in other cases, a semiconductor material may be formed first in order to electrically connect end portions of the fins at both sides of the gate electrode structure in order to provide respective drain and source areas. For this purpose, the end portions of the fins 110 not covered by the gate electrode structure may be exposed by removing the gate dielectric material 121, which may be accomplished by well-established etch recipes, for instance on the basis of hydrofluoric acid and the like. Thereafter, the exposed surface portions of the fins 110 may be prepared for a subsequent selective epitaxial growth process, which may involve well-established cleaning processes and the like.
A resulting FinFET device 100 is shown in a 3D view in FIG. 1c. Each of the fins 110 in combination with the common gate electrode structure 120 may represent a single transistor cell of the device 100. In principle, the fins 110 may exhibit an appropriate dopant concentration so as to define corresponding drain and source areas in each of the fins 110, while, in other strategies, corresponding drain and source regions may be formed in a later stage after connecting the end portions of the fins 110 by growing a further semiconductor material so as to fill the spacing between the individual fins 110.
However, the effective channel lengths and, in particular, the channel height extensions (in the direction perpendicular to the substrate whereupon the FinFET is formed) of conventionally formed FinFETs, and thereby the drive currents, are limited. There is a general need to improve the overall performance of FinFETs of the art, in particular, in view of the ongoing demand for size reductions.
In view of the situation described above, the present disclosure provides FinFET devices that may exhibit improved performance characteristics as compared to prior art FinFET devices.